Multilevel interconnect structure with low-k dielectric and method of fabricating the structure

ABSTRACT

A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the photoresist layer to fill the openings and then removing the photoresist layer by, for example, ashing. The metal layer is supported by the metal which filled the openings formed in the photoresist.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a continuation-in-part of U.S. applicationSer. No. 08/874,389, filed on Jun. 13, 1997. U.S. application Ser. No.08/874,389 is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor multilevelinterconnect structures exhibiting a low RC time delay and which takeless time to fabricate. More particularly, the present invention relatesto a semiconductor multilevel interconnect structure made of metalshaving a low resistivity and insulators having a low dielectric constantk, and to a method of fabricating the multilevel interconnect structurewith a low-k dielectric.

[0003] It is common in the semiconductor art to use layers of metal,polysilicon, or another conductor to conduct current between varioussemiconductor structures with an integrated circuit, and to externalterminals for the integrated circuit, by means of conductive vias.

[0004] When a metal is used to form the interconnect layers ofconductors, the metal is usually deposited on the semiconductor bysputtering, chemical vapor deposition (CVD), or evaporation. The CVDprocess forms a non-volatile solid film on a substrate by the reactionof vapor phase chemicals that contain the desired constituents. Themetals that are commonly used for the interconnect layers are aluminumand its alloys, although other conductive metals and materials can alsobe used, with copper being a recent preference. The metal layers aretypically deposited over dielectric materials, such as silicon dioxide.Parallel plate capacitive effects can be observed with a conductiveinterconnect structure. The capacitance for adjacent conductive layerscan be represented as: $C = \frac{{ɛ\quad}_{o}{ɛ\quad}_{ins}A}{D}$

[0005] where

[0006] D=SiO₂ thickness

[0007] A Area of plates (adjacent conductors)

[0008] ε_(o)=Permittivity of free space

[0009] ε_(ins)=Relative Permittivity of SiO₂

[0010] This capacitance at a metal interconnected plate increases as thedensity of the integrated circuits increases.

[0011] Also, the line resistance due to the metal layers increases asthe density of the integrated circuits increases. The resistance of asheet of conducting material is given as:$R_{s} = \underset{tW}{r\underset{\_}{L}}$

[0012] where

[0013] r=Material resistivity

[0014] L=Material length

[0015] t=Material thickness

[0016] W=Material width

[0017] Thus, the time delay caused by the product of the line resistanceand the capacitance (RC delay) becomes increasingly critical as devicesize decreases and which circuit speed increases.

[0018] An attempt to reduce the capacitance association withinterconnect layers deposited on dielectric materials is shown in Togoet al., “A Gate-side Air-gap Structure (GAS) to Reduce the ParasiticCapacitance in MOSFETs”, 1996 Symposium on VLSI Technology, Digest ofTechnical Papers, pp. 38-39. Togo et al outlines a transistor structurein which the sidewalls of the gate structure are surrounded by an airgap. A silicon nitride sidewall is first fabricated that surrounds thegate. A layer of silicon dioxide is formed around the silicon nitridesidewall. The silicon nitride sidewall is removed by a wet etchingprocess to form an air gap between the gate structure and the silicondioxide.

[0019] Another attempt to reduce the capacitance associated withinterconnect layers deposited on silicon is shown in Anand et al, “NURA:A Feasible, Gas-Dielectric Interconnect Process”, 1996 Symposium on VLSITechnology, Digest of Technical Papers, pp. 83-83. Anand et al outlinesa metal interconnect structure in which layers of a gas are formedbetween thin layers of silicon dioxide. The thin layers of silicondioxide have metal interconnect layers deposited on them. The processbegins when layers of carbon are formed on a surface and trenches areformed for future interconnections. An interconnect metal layer isformed in the carbon trenches and a thin layer of silicon dioxide issputter-deposited. Oxygen is then furnace a shed into the carbon layerthrough diffusion and the oxygen reacts with the carbon to form carbondioxide. This process is repeated to form the interconnect structure ofthe device under fabrication.

[0020] Although Togo et al claims to reduce the capacitance associatedwith the interconnect layers by reducing the dielectric constant of thematerials between the interconnect layers, Togo et al only provides alow dielectric material (air) around the gate contact of a transistor.Also, Togo et al does not disclose an interconnect structure that hasreduced resistivity.

[0021] Likewise, even though Anand et al claims to reduce thecapacitance associated with the interconnect layers by reducing thedielectric constant of the materials between the interconnect layers,Anand et al adds complexity to the semiconductor fabrication processbecause carbon is used in the process, which is not typically used inthe manufacture of semiconductor devices. The method of Anand et al doesnot disclose an interconnect structure that has reduced resistivity.

[0022] Thus, the need exists for a semiconductor interconnect structurewith reduced capacitance and reduced resistivity, thereby decreasing theRC time delay associated with the interconnect layers. The need alsoexists for a method of fabricating such a structure using standardfabrication steps in conjunction with commercially available processingequipment.

[0023] Also, steady improvements in integrated circuit density andperformance have been achieved over the past two decades by transistorscaling. While the scaling continues to be necessary, metalinterconnects are now becoming a significant limiting factor and are asimportant as transistors in determining ULSI density and performance. Asdiscussed by M.T. Bohr in “Interconnect Scaling-The Real Limiter to HighPerformance ULSI”, 1995 IEDM Technical Digest, p. 241-244, eachtechnology generation represents a 0.7× reduction in feature size, andinterconnect delay degrades at a rate of 2× per generation assuming aconstant metal aspect ratio and no change in conductor or dielectricmaterials.

[0024] As the feature size goes down so does insulator thickness so theinterconnect capacitance remains the same while the wiring resistancedoubles. Interconnect delay for large high-frequency chips is already asignificant portion of the clock cycle time and will soon exceed thecycle time requirements if traditional interconnect scaling iscontinued.

[0025] Also the increasing density/complexity of circuits and speed ofoperation result in excessive power dissipation in digital switching andclocking circuits. The power dissipation is approximately representedby:

Power˜CV²f

[0026] where

[0027] C=the capacitance of the clock line,

[0028] V=the voltage swing, and

[0029] f=the clock frequency.

[0030] As noted by L. Maliniak, “DAC attacks designer issues”,Electronic Design, vol. 43, p. 66, Jun. 12, 1995, clock distribution canaccount for up to 40% of the total power dissipation in high-performancewireless computing and communication systems.

[0031] Similar considerations apply in calculating the power dissipationof digital switching circuits.

SUMMARY OF THE INVENTION

[0032] As attempts to provide higher speed small sized devices continuesit is becoming increasingly difficult to achieve desired objectivesbecause of RC effects and the complexity and time of device fabricationrequired to reduce such effects.

[0033] In accordance with the present invention, the deposition time ofdielectric films in a multilevel interconnect structure is minimized byreducing the number of dielectric deposition cycles. In a preferredembodiment the number of dielectric deposition cycles is reduced to one.Instead of depositing an interlayer dielectric layer after each metallayer, the multilevel interconnect structure is built using sacrificialphotoresist layers, followed by a single dielectric layer depositioncycle.

[0034] Thus, the present invention is directed to a multilevelinterconnect semiconductor structure having a low-k dielectric outercoating and to a method of fabricating the structure. The interconnectstructure is fabricated using typical fabrication steps, materials, andmachines.

[0035] The method, in its broadest form, comprises the steps ofdepositing a layer of photoresist on a substrate assembly, etching thephotoresist to form openings, depositing a metal layer on thephotoresist layer so as to fill the openings, and removing thephotoresist layer by, for example, ashing in an oxygen plasma. An upperlevel conductive metal layer is supported by the metal which filled theopenings formed in the photoresist to form a multilevel metallizedinterconnect structure. The upper level of the interconnect structure isthen coated with a low-k dielectric film.

[0036] The conductive layers preferably comprise copper, and the singledielectric deposition is preferably in the form of a layer of an aerogelor xerogel.

[0037] The present invention represents significant advantages over theprior art. Because the air (gas) spaces between the conductiveinterconnect layers are formed by removing layers of photoresist, noextra material need be introduced into the semiconductor manufacturingprocess. Also, because the conductive interconnect layers are surroundedby air, the plate capacitance of the interconnect structure is reduced.Furthermore, because a low resistive material such as copper is used forthe conductive interconnect layers, the layers may be electroplated orelectroless plated at low temperatures.

[0038] Reducing the dielectric constant of the inter-level dielectricimproves interconnect signal delay and reduces AC power consumption.Also, the total process time just for the deposition of dielectrics atmultiple levels can exceed 200 hours. Therefore, reducing the time forthe deposition of dielectric layers is a significant advantage.

[0039] The above and other features and advantages of the invention willbe more readily understood from the following detailed description ofthe invention which is provided in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040]FIG. 1 is a cross-sectional view of a substrate assembly on whicha layer of photoresist has been deposited, masked, hardened, and etched;

[0041]FIG. 2 is a cross-sectional view of the substrate assembly of FIG.1 on which a bilayer adhesion promoter/diffusion barrier has beendeposited on the etched photoresist layer;

[0042]FIG. 3 is a cross-sectional view of the substrate assembly of FIG.2 on which a metal layer has been deposited on the bilayer adhesionpromoter/diffusion barrier;

[0043]FIG. 4 is a cross-sectional view of the substrate assembly of FIG.3 following removal of excess metal from the metal layer to form metalplugs;

[0044]FIG. 5 is a cross-sectional view of the substrate assembly of FIG.4 on which a photoresist layer has been deposited, masked, hardened, andetched on the promoter layer and metal plug;

[0045]FIG. 6 is a cross-sectional view of the substrate assembly of FIG.5 on which a bilayer adhesion promoter/diffusion barrier and a firstmetal layer have been deposited on the etched photoresist layer;

[0046]FIG. 7 is a cross-sectional view of the substrate assembly of FIG.6 following the removal of excess metal from the first metal layer;

[0047]FIG. 8 is a cross sectional view of the substrate assembly of FIG.7 following the addition of a photoresist layer, a bilayer adhesionpromoter/diffusion barrier, a metal plug, and a second metal layer ontothe etched photoresist layer and the first metal layer;

[0048]FIG. 9 is a cross-sectional view of the substrate assembly of FIG.8 following the removal of the photoresist layers to form gaps betweenthe bilayers of adhesion promoter/diffusion barrier and the underlyingsubstrate assembly;

[0049]FIG. 10 is a cross-sectional view of another embodiment of asubstrate assembly on which a layer of photoresist has been deposited,masked, hardened, and etched;

[0050]FIG. 11 is a cross-sectional view of the substrate assembly ofFIG. 10 on which a bilayer adhesion promoter/diffusion barrier has beendeposited on the layer of photoresist and on which a metal layer hasbeen deposited on the bilayer; and

[0051]FIG. 12 is a cross-sectional view of the substrate assembly ofFIG. 11 following removal of excess metal from the metal layer to formmetal plugs and then coated with a low-k dielectric film.

DETAILED DESCRIPTION OF THE INVENTION

[0052] The discussion below refers to a bilayer adhesionpromoter/diffusion barrier. As used herein, a bilayer adhesionpromoter/diffusion barrier means that the bilayer functions to enhanceadhesion of the metal layer to the structure and to minimize thediffusion of metal from the metal layer into dielectric material.

[0053] The present invention relates to the provision of an interconnectstructure which has an improved RC response for high speed signaltransmission and which is relatively easy to construct. By way ofbackground, methods of depositing aerogels, xerogels and otherspin-coated dielectric materials used as interconnect dielectronicsoften require complicated, extensive processing. For example, thelow-density SiO₂ xerogel films which are often used to insulate aninterconnect structure are prepared by a sol-gel process which offersthe recise control of microstructure (pore size, pore volume, andsurface area). A typical process involves a spin coating (20 sec),aging/washing (24 hours), surface modification (12 hours), anddrying/thermal treatment (2 hours). See J-K Hong et al, “The effect ofsol viscosity on the sol-gel derived low-density Sio₂ xerogel film forintermetal dielectric application”, Thin Solid Films, vol.332,p.449-454, 1998, which is incorporated herein by reference. For futuremicroprocessors requiring 6 to 7 levels of metallization, the totalprocess time could easily exceed 200 hours just for the deposition ofdielectrics.

[0054] In accordance with the present invention, the deposition time ofdielectric films is minimized by reducing the number of dielectricdeposition cycles. In a preferred embodiment the number of dielectricdeposition cycles is reduced to one. Instead of depositing interlayerdielectric after each metal layer, the multilayer metallization is builtusing sacrificial photoresist layers, followed by a single dielectricdeposition cycle. In addition to reducing manufacturing time, theresultant interconnect structure has good high speed signal transmissionproperties because of lowered RC effects.

[0055] Low-k dielectric materials, including fluorine-doped SiO₂,polymers and aerogels which could be used as an interconnect insulatorare shown in the following Table. As shown, low-k dielectrics have adielectric constant less than [or equal to] 4.5. TABLE* MATERIAL METHODDIELECTRIC CONSTANT DEPOSITION Undoped plasma SiO2** 3.9-4.5 CVD, . . .Fluorine doped SiO2 ˜3.5 CVD Flowable Oxide ˜3.5 Spin-on Spin-on glass2.8-3.0 Spin-on Porous SiO2 <2.0 Spin-on Polyimide 3.0-3.7 Spin-onPolyimide siloxane 2.6-2.7 Spin-on Polysilsesquioxane (Si polymer)2.7-3.0 Spin-on Benzocyclobutene (BCB) 2.5-2.7 Spin-on Parylene N2.6-2.7 CVD Fluorinated Polyimide ˜2.5 Spin-on Poly(Olefins) 2.4-2.6Spin-on Parylene F 2.3-2.4 CVD Poly-Naphthalene ˜2.3 CVD Amorphousteflon 1.9-2.1 Spin-on Polymer foams  <2-3.0 Spin-on Aerogels 1.1-2.0Spin-on Air 1.0

[0056] Of the low-k dielectrics reported in the Table, aerogels possessthe lowest dielectric constant. Aerogels and also xerogels have adielectric constant of between 1.1 and 2.0, 35 and also the highestthermal stability (900° C.). Therefore, aerogels and xerogels arepreferred for use in accordance with the present invention in ULSItechnology. It should also be noted that air has the lowest dielectricconstant of 1.0.

[0057] A suitable dielectric material for use in the present 4.0invention has a dielectric constant of from about 1 to about 2.5. Apreferred dielectric constant range is from about 1 to about 2.0. Otherproperties of suitable low k-material are no or low moisture absorption,thermal stability, and mechanical stability to be compatible withchem-mechanical planarization process. The material should be compatiblewith low & high temperature chip pull off, such that it contains noresidues that may outgas during later process at high temperature or atpull off. The material also preferably has a glass transition (Tg)temperature of >350° C., a high breakdown field strength of >5MV/cm, anda low leakage current of <1 nA @ use voltage.

[0058] Following is an embodiment of the method of fabricating amultilevel interconnect structure with a low-k dielectric material inaccordance with the present invention.

[0059] With reference to FIG. 1, there is shown a cross-sectional viewof a typical substrate assembly 30. The assembly 30 includes a substratelayer 32, which is the lowest layer of semiconductor material on a waferand additional layers or structures formed thereon. A Local Oxidation ofSilicon (LOCOS) process is performed on the substrate layer 32 toprovide a layer of gate oxide 33 and device separating field oxideregions 34 formed of, for example, SiO₂. A polysilicon layer 36 isdeposited and etched to provide a contact area, typically for the gateterminal G of a transistor. An isolation insulating spacer 37 may beformed along the sides of layer 36 using conventional techniques.Impurities are diffused into the substrate 34 through suitable masks toform diffusion areas 38. The diffusion areas 38 provide the source S anddrain D terminals of the transistor. Silicide layers 40 are formed onthe diffusion areas 38. The silicide layers 40 are formed by depositinga refractory metal such as titanium, platinum, palladium, cobalt, ortungsten on polysilicon. The metal/silicon alloy is then sintered toform the silicide layers 40.

[0060] After the silicide layers 40 are formed, the substrate assembly30 is then ready for metallization. A first layer of photoresist 42 isdeposited on the substrate assembly 30 and is masked, hardened, andetched to define openings 43 for contact plugs. The photoresist layer 42is hardened by baking the substrate assembly 30 at a temperaturetypically below 100° C.

[0061] Since copper tends to diffuse into a dielectric material, it ispreferred to counter such diffusion with a diffusion barrier. FIG. 2shows the substrate assembly 30 of FIG. 1 after a bilayer adhesionpromoter/diffusion barrier 44 is deposited by, for example, sputteringonto the surface of the etched photoresist layer 42. Ionized sputteringis preferred to provide effective coverage of the sidewalls of deepopenings. A chemical vapor deposition (CVD) process may also be used todeposit the bilayer adhesion promoter/diffusion barrier 44.

[0062] The bilayer adhesion promoter/diffusion barrier 44 can be, amongother substances, titanium/copper, chromium/copper, titaniumnitride/copper, tantalum/copper, W/copper or WN/copper. Typicalthickness is 10 to 20 nm for the adhesive layer and 20 to 30 nm for thecopper to be used as a plating base.

[0063] The bilayer can be deposited as two layers. Alternatively, thebilayer can be simultaneously deposited from two different sources,e,g., two targets would be used in an ionized sputtering process, or twogas sources could be used in a CVD process.

[0064] The deposition of adhesion promotor/diffusion barrier 44 may beeliminated if a CVD process is used as discussed below for deposition ofconducting metal such as copper and aluminum alloys. This step may alsobe eliminated when deposition techniques such as high-rate magnetronsputtering or evaporation are employed to produce a conducting metallayer as described below.

[0065] As shown in FIG. 3, a metal layer 46 is formed, for example, byplating on the bilayer adhesion promoter/diffusion barrier 44. The metallayer 46 is preferably cooper, which can be electroplated or electrolessplated on the substrate assembly 30 at a process temperature around 30°C. A thick copper film (0.5 to 1.0 micron thick) preferably isdeposited.

[0066] The metal layer 46 may also be deposited using a CVD process.

[0067] As noted, if the metal layer 46 is deposited by a CVD process orby high-rate magnetron sputtering or by evaporation, the bilayeradhesion promotor/diffusion barrier 44 may optionally be eliminated.

[0068] The excess metal from the metal layer 46 and the excess bilayeradhesion promoter/diffusion barrier 44 are next removed throughmechanical abrasion, for example, by chemical mechanical polishing(CMP), to form metal plugs 48, as shown in FIG. 4. The substrateassembly 30 is planar after the removal of the excess metal. Theremaining portions of the bilayer adhesion promoter/barrier 44 definereceptacles 45, in which the metal plugs 48 are located.

[0069] A second photoresist layer 50 is next deposited onto the bilayeradhesion promoter/barrier 44 and the metal plugs 48 as shown in FIG. 5.The photoresist layer 50 is masked, hardened, and etched to defineopenings 51 for a metal layer which is aligned with the plugs 48.

[0070]FIG. 6 shows a bilayer adhesion promoter/barrier 52 deposited onthe etched photoresist layer 50 and metal plugs 48 and a second metallayer 54 plated on the bilayer adhesion promoter/barrier 52. A portionof the metal fills the openings 51 forming contacts 53. The second metallayer 54 is deposited, for example, by electroplating using a platingbase. Alternately, a plating base is not needed when metal layer 54 isdeposited by CVD, high-rate magnetron sputtering, or evaporation, as wasnoted above for metal layer 46.

[0071] As shown in FIG. 7, excess metal from the second metal layer 54and excess bilayer adhesion promoter/barrier 52 are next removed bymechanical abrasion, such as chemical mechanical polishing (CMP). Thus,the second metal layer 54 forms contacts 53 and the resulting substrateassembly is planar.

[0072]FIG. 8 illustrates the substrate assembly 30 of FIG. 7 after (i)photoresist layer 62 is deposited, hardened and etched, (ii) a bilayeradhesion promoter/diffusion barrier 64 is deposited and CMP planarized,and (iii) a third metal layer 70 is deposited onto the substrateassembly 30. The substrate assembly 30 in FIG. 8 has been mechanicallypolished to remove the excess metal layer 70 and the remaining portionsof the bilayer adhesion promoter/diffusion barrier 64 to form metal plug66 in receptacle 68. The third metal layer 70 forms contact 72. Thesurface 54 is in contact with another metal plug and receptacle or otherassembly component which is not shown in the cross-sectional view ofFIG. 8. The steps of applying a patterned photoresist layer, a bilayeradhesion promotor/diffusion barrier 52 (sometimes optional as notedabove), and another metal layer, as described with reference to FIGS. 5to 8, can be repeated to build up more metal layers, as needed.

[0073]FIG. 9 shows a resulting substrate assembly 30 of FIG. 8 with thefirst metal layer 48, the second metal layer 54 and the third metallayer 70 formed. The photoresist layers 42, 50 and 62 are next removedby, for example, ashing in oxygen plasma to form air gaps 56. The metallayers 54 and 70 are supported by columns 60 and 74 formed by thecombination of the metal plugs 48 and the contacts 53 and 72. The airgaps 56 have a dielectric constant of 1, thereby reducing the residualcapacitance of the resulting interconnected structure. By selectingappropriate metal conductors which have a low resistance, such ascopper, the overall RC time constant of the resulting interconnectedstructure is reduced.

[0074] At this stage, a suitable bilayer adhesion promoter/diffusionbarrier may deposited over the entire structure in one step by, forexample, sputtering. Ionized sputtering is preferred to provideeffective coverage of the sidewalls of deep openings. Also, a chemicalvapor deposition (CVD) process or electroless' plating may be used todeposit the bilayer adhesion promoter/diffusion barrier.

[0075] The multilevel metallized interconnect structure of FIG. 9 isthen coated with a low-k dielectric film 94 in one step. 15 This onestep may be a sol-gel method, a CVD, a spin-on process, or a vapordeposition process. If needed, the low-k dielectric film 94 isplanarized. As noted, preferred materials for film 94 are those listedin the table above having a low dielectric constant, preferably betweenabout 1 20 and about 2.5 and most preferably between about 1 and about2, with aerogels and xerogels being particularly prefered. Anotherembodiment of the invention is shown in FIGS. 10 to 12. In thisembodiment the invention is applied to creating upper levels ofinterconnects which may be used for long signal interconnections andclock distribution.

[0076] With reference to FIG. 10, there is shown a cross-sectional viewof a typical substrate assembly 80 having upper levels of interconnectedmetal which are used for long signal interconnections and clockdistribution. The assembly 80 includes a lower insulation layer 82 ofSiO₂ which is applied to the upper surface of a fabricated circuit andwhich has metal contacts 84,86 formed therein.

[0077] Metal contacts 84, 86 may, if desired, be formed using thetechniques described above with reference to FIGS. 1-9 for underlyingmetal interconnect layers. Alternatively, conventional metalinterconnect layers may reside below contacts 84, 86. Diffusion barrierlayers 87,89 are deposited on the surface of insulation layer 82 and thelower planar metal contacts 84,86. For example, a layer 89 of Si₃N₄ isapplied over the lower oxide insulator 82 of SiO₂, and a layer 87 of TiNis applied over the lower metal contacts 84,86.

[0078] A first layer of photoresist 88 is deposited on the substrateassembly 80 and is masked, hardened, and etched to define openings 90for contact plugs.

[0079]FIG. 11 shows the substrate assembly 80 of FIG. 10 after a bilayeradhesion promoter/diffusion barrier 91 is deposited by, for example,sputtering onto the surface of the etched photoresist layer 88.

[0080] As shown in FIG. 11, a metal layer 92 is also formed, forexample, by plating on the bilayer adhesion promoter/diffusion barrier91. The metal layer 92 is preferably cooper, which can be electroplatedor electroless plated on the substrate assembly 80 at a processtemperature around 30° C. A thick copper film (0.5 to 1.0 micron thick)preferably is deposited.

[0081] The metal layer 46 may also be deposited using a chemical vapordeposition (CVD) process. As with the previous embodiment the bilayeradhesion promoter/diffusion barrier 91 may be omitted or optionallyused, with a CVD metal layer process or if the metal is deposited byhigh-rate magnetron sputtering or if evaboration is used.

[0082] With reference to FIG. 12, the excess metal from the metal layer92 and the excess bilayer adhesion promoter/diffusion barrier 91 areremoved through mechanical abrasion, for example, by chemical mechanicalpolishing (CMP), to form metal plugs 93,94. The substrate assembly 80 isplanar after the removal of the excess metal. The remaining portions ofthe bilayer adhesion promoter/diffusion barrier 91 define receptacles,in which the metal plugs 93,94 are located. The steps of applying apatterned photoresist layer, a bilayer adhesion promoter/diffusionbarrier and another metal layer, as described with reference to FIGS. 5to 8, can be repeated to build up more layers of metals as needed. Whenall metal layers are applied the photoresist layers are removed byashing.

[0083] The multilevel metallized interconnect structure (FIG. 12) iscoated with a low-k dielectric film 95 in one step. This one step may bea sol-gel method, a CVD process, a spin-on process, or a vapordeposition process. If needed, the low-k dielectric film 95 isplanarized. This method allows the capacitance of long, high-speedlines, where it is most critical, to be significantly reduced throughthe use of a low-k dielectric.

[0084] The significant advantages of fabricating a multilevelinterconnect structure with a coating of low-k dielectric in accordancewith the present invention are that the time for depositing thedielectric is substantially reduced. The use of low-k dielectrics incontact with interconnection and clock lines reduce RC signal delays andpower dissipation.

[0085] The present invention may be employed to fabricate aninterconnect structure for use in any type of integrated circuit deviceincluding, but not limited to, microprocessors, logic devices, DSP andmemory circuits, such as DRAMS, SRAMS, SDRAMS, etc.

[0086] It is to be understood that the figures have been simplified toillustrate only those aspects of semiconductor topography which arerelevant, and some of the dimensions have been exaggerated to convey aclear understanding of the present invention, while eliminating, for thepurposes of clarity, some elements normally found on or in asemiconductor structure. Those of ordinary skill in the art willrecognize that other elements and process steps are required to producean operational semiconductor. However, because such elements and processsteps are well known in the art, and because they do not further aid inthe understanding of the present invention, a discussion of suchelements is not provided herein.

[0087] Although the present invention has been described with referenceto preferred embodiments, it is to be understood that modifications andvariations may be made without departing from the spirit and scope ofthis invention, as those skilled in the art will readily understand. Allsuch modifications and variations are considered to be part of theinvention. Accordingly, the invention is not limited by the foregoingdescription, but is only limited by the scope of the appended claims.

What is claimed is:
 1. A method of fabricating a semiconductorinterconnect structure comprising the steps of: depositing a layer ofphotoresist on a substrate assembly; etching the photoresist layer toform a plurality of openings; depositing a metal layer on thephotoresist layer to fill the openings formed in the photoresist layer;removing the photoresist layer such that the metal layer is supported bythe metal which fills the openings formed in the photoresist; anddepositing a low-k dielectric constant film on the interconnectstructure.
 2. The method of claim 1 wherein the low-k dielectric film isdeposited on said metal layer.
 3. The method of claim 1 furthercomprising the step of depositing a bilayer adhesion promoter/diffusionbarrier prior to the step of depositing said metal layer.
 4. The methodof claim 3 wherein said bilayer adhesion promoter/diffusion barrier isdeposited by an ionized sputtering process.
 5. The method of claim 3wherein said bilayer adhesion promoter/diffusion barrier is deposited bya chemical vapor depositing process.
 6. The method of claim 1 whereinsaid metal layer comprises a copper containing material deposited by anelectroplating process.
 7. The method of claim 1 wherein said metallayer comprises a copper containing material deposited by an electrolessplating process.
 8. The method of claim 1 wherein said metal layercomprises a copper containing material deposited by a chemical vapordepositing process.
 9. The method of claim 1 wherein said resist layeris removed by ashing in a plasma.
 10. The method of claim 1 wherein saidbilayer adhesion promoter/diffusion barrier is selected from the groupconsisting of titanium/copper, chromium/copper, titanium nitride/copper,tantalum/copper, W/copper and WN/copper.
 11. The method of claim 1wherein said bilayer adhesion promoter/diffusion barrier is selectedfrom the group consisting of W/copper and WN/copper.
 12. The method ofclaim 1 wherein said dielectric film has a dielectric constant of fromabout 1 to about 2.5.
 13. The method of claim 1 wherein said dielectricfilm has a dielectric constant of from about 1 to about 2.0.
 14. Themethod of claim 1 wherein said dielectric film is selected from thegroup consisting of aerogels and xerogels.
 15. The method of claim 1wherein the metal layer comprises a copper containing material and has athickness of from about 0.5 micron to about 1.0 micron.
 16. A method offabricating a multilevel semiconductor interconnect structure comprisingthe steps of: (i) depositing a layer of photoresist on a substrateassembly; (ii) etching the photoresist layer to form a plurality ofopenings; (iii) depositing a metal layer on the photoresist layer tofill the openings formed in the photoresist layer; (iv) repeating thesteps of (i) depositing a layer of photoresist, (ii) etching thephotoresist layer and (iii) depositing a metal layer until apredetermined number of metal layers levels are formed; (v) removing thephotoresist layers such that the metal layers are supported by the metalwhich filled the openings formed in the photoresist; and (vi) depositinga low-k dielectric film on the interconnect structure.
 17. The method ofclaim 16 wherein said resist layers are removed by ashing a plasma intosaid interconnect structure.
 18. The method of claim 16 wherein saidbilayer adhesion promoter/diffusion barriers are selected from the groupconsisting of titanium/copper, chromium/copper, titanium nitride/copper,tantalum/copper, W/copper and WN/copper.
 19. The method of claim 16wherein said bilayer adhesion promoter/diffusion barriers are selectedfrom the group consisting of W/copper and WN/copper.
 20. The method ofclaim 16 wherein said dielectric film has a dielectric constant of fromabout 1 to about 2.5.
 21. The method of claim 16 wherein said dielectricfilms has a dielectric constant of from about 1 to about 2.0.
 22. Themethod of claim 16 wherein said dielectric film is selected from thegroup consisting of aerogels and xerogels.
 23. The method of claim 16wherein the metal layers are copper and have a thickness of from about0.5 micron to about 1.0 micron.
 24. A method of claim 16 wherein saidmetal layers are formed of a copper containing material.
 25. Amultilevel semiconductor interconnect structure fabricated by the stepscomprising: (i) depositing a layer of photoresist on a substrateassembly; (ii) etching the photoresist layer to form a plurality ofopenings; (iii) depositing a metal layer on the photoresist layer andfilling the openings formed in the photoresist layer; (iv) repeating thesteps of (i) depositing a layer of photoresist, (ii) etching thephotoresist layer and (iii) depositing a metal layer until apredetermined number of metal layers are formed; (v) removing thephotoresist layers such that the metal layers are supported by the metalwhich filled the openings formed in the photoresist; and (vi) depositinga low-k dielectric film on the interconnect structure.
 26. The structureof claim 25 further comprising the step of depositing a bilayer adhesionpromoter/diffusion barrier on the photoresist layer prior to the step ofdepositing said metal layer.
 27. The structure of claim 26 wherein saidbilayer adhesion promoter/diffusion barrier is selected from the groupconsisting of titanium/copper, chromium/copper, titanium nitride/copper,tantalum/copper, W/copper and WN/copper.
 28. The structure of claim 27wherein said bilayer adhesion promoter/diffusion barrier is selectedfrom the group consisting of W/copper and WN/copper.
 29. The structureof claim 25 wherein said dielectric film has a dielectric constant offrom about 1 to about 2.5.
 30. The structure of claim 25 wherein saiddielectric films has a dielectric constant of from about 1 to about 2.0.31. The structure of claim 25 wherein said dielectric film is selectedfrom the group consisting of aerogels and xerogels.
 32. The structure ofclaim 25 wherein the metal layers are copper and have a thickness offrom about 0.5 micron to about 1.0 micron.
 33. A semiconductor devicecomprising: a substrate assembly; and at least one interconnectstructure on said substrate assembly, said interconnect structurecomprising: a first plurality of metal plugs formed above said substrateassembly; a metal layer having a portion elevated above said substrateassembly and a portion defining a second plurality of metal plugs formedbelow said metal layer and in electrical contact with a respective onesof said first plurality of metal plugs such that said metal layer is inelectrical contact with the substrate assembly, said plurality of metalplugs supporting said elevated portion of said metal layer; a gassurrounding said first and second plurality of metal plugs; and a low-kdielectric film on said metal layer.
 34. The semiconductor device ofclaim 33 wherein said gas is air.
 35. A semiconductor device of claim 33wherein said low-k dielectric film has a dielectric constant of about 1to about 2.5.
 36. A semiconductor device of claim 35 wherein said low-kdielectric film has a dielectric constant of about 1 to 2.0.
 37. Asemiconductor device of claim 33 wherein said low-k dielectric filmcomprises one of an aerogel and a xerogel.
 38. A semiconductor device ofclaim 33 wherein said metal plugs and metal layer are formed of a coppercontaining material.
 39. A semiconductor device of claim 33 wherein saidmetal layer has a thickness of from about 0.5 micron to about 1.0micron.bstrate, and a diffusion barrier layer of TiN is provided oversaid metal contacts.
 40. A semiconductor device comprising: a substrateassembly; and at least one interconnect structure on said substrateassembly, said interconnect structure comprising: a first bilayeradhesion promoter/diffusion barrier defining a plurality of firstreceptacles; a plurality of metal plugs formed in said plurality offirst receptacles; a second bilayer adhesion promoter/diffusion barrierdefining a plurality of second receptacles above said metal plugs; ametal layer having a portion elevated above said substrate assembly anda portion filling said plurality of second receptacles such that saidmetal layer is in electrical contact with the substrate assembly, saidmetal filling said second plurality of receptacles and said plurality ofmetal plugs supporting said elevated portion of said metal layer with agas surrounding said first and second receptacles; and a low-kdielectric film on said metal layer.
 41. A semiconductor device of claim40 wherein said gas is air.
 42. A semiconductor device of claim 41wherein said low-k dielectric film has a dielectric constant of about 1to about 2.5.
 43. A semiconductor device of claim 41 wherein said low-kdielectric film has a dielectric constant of about 1 to 2.0.
 44. Asemiconductor device of claim 43 wherein said low-k dielectric filmcomprises one of an aerogel and a xerogel.
 45. A semiconductor device ofclaim 41 wherein said metal plugs at metal layer are formed of a coppercontaining material.
 46. A semiconductor device of claim 41 where saidmetal layer has a thickness of from about 0.5 micron to about 1.0micron. lower planar metal contacts recessed in said lower insulationsubstrate, and respective diffusion barrier layers deposited on saidlower insulation substrate and said metal contacts.
 47. Thesemiconductor device of claim 41 wherein a diffusion barrier layer ofSi₃N₄ is provided over said lower insulation substrate, and a diffusionbarrier layer of TiN is provided over said metal contacts.
 48. Thesemiconductor device of claim 41 wherein said bilayer adhesionpromoter/diffusion barriers are selected from the group consisting oftitanium/copper, chromium/copper, titanium nitride/copper,tantalum/copper, W/copper and WN/copper.
 49. The semiconductor device ofclaim 41 wherein said dielectric film has a dielectric constant of fromabout 1 to about 2.5.
 50. The semiconductor device of claim 41 whereinsaid dielectric films has a dielectric constant of from about 1 to about2.0.
 51. The semiconductor device of claim 41 wherein said dielectricfilm is selected from the group consisting of aerogels and xerogels. 52.The semiconductor device of claim 41 wherein the metal layer comprisecopper and has a thickness of from about 0.5 micron to about 1.0 micron.53. The semiconductor device of claim 41 wherein said substrate assemblycomprises a lower insulation substrate, a plurality of lower planarmetal contacts recessed in said lower insulation substrate, andrespective diffusion barrier layers deposited on said lower insulationsubstrate and said metal contacts.
 54. The semiconductor device of claim53 wherein a diffusion barrier layer of Si₃N₄ is provided over saidlower insulation substrate, and a diffusion barrier layer of TiN isprovided over said metal contacts.
 55. The semiconductor device of claim41 wherein said first and second bilayer adhesion promoter/diffusionbarriers are selected from the group consisting of W/copper andWN/copper.
 56. The semiconductor device of claim 41 wherein saiddielectric film has a dielectric constant of from about 1 to about 2.5.57. The semiconductor device of claim 41 wherein said dielectric filmshas a dielectric constant of from about 1 to about 2.0.
 58. Thesemiconductor device of claim 41 wherein said dielectric film isselected from the group consisting of aerogels and xerogels.
 59. Thesemiconductor device of claim 41 wherein the metal layer comprise copperand has a thickness of from about 0.5 micron to about 1.0 micron.